Semiconductor Engineering

Scalable End-To-End Test Solutions For Today’s Complex SoCs

Left-shifting DFT, scalable tests from manufacturing to the field, enabling system-level tests for in-field debug.
Design-Reuse

Pentek Adds Pulse Compression IP Core to GateFlow Library for Xilinx Virtex FPGAs

Integrated Core Provides FPGA Alternative to DSPs in Radar Applications Flexible Design Offers 24 Variations to Match System Needs Optimized for Maximum Throughput or Minimum Resource Utilization ...
Design-Reuse

How to evaluate test compression methods

For the past five years, the cost of test has prevailed as the hottest topic in test. During this period, automated test equipment (ATE) has made a dramatic move towards low-cost design for test (DFT) ...
InfoWorld

How to use Brotli for response compression in ASP.Net Core

Take advantage of ASP.Net Core’s support for response compression middleware to get more compression in less time using Brotli When working with RESTful services that leverage the ASP.Net Core Web API ...
Semiconductor Engineering

Squeezing Out More Test Compression

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...
EDN

Design for test boot camp, part 2: Test compression

The size of designs continues to grow and IC manufacturers are pushing for higher test quality, especially in mission-critical applications such as transportation and medicine. More advanced nodes ...
Electronic Design

The Benefits—And Hazards—Of Scan Compression

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...