Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Design-Reuse

Mentor Graphics Announces Interoperability of Serial ATA Intellectual Property Solution

WILSONVILLE, Ore., December 21, 2007 – Mentor Graphics Corporation today announced successful interoperability testing of Mentor’s Serial ATA (SATA) Host/Device IP controllers integrated with the ...
EDN

Mentor Graphics inFact Tool provides plug-and-play interoperability with OVM

The folks at Mentor Graphics say that the inFact intelligent testbench automation tool, which applies universally to FPGA and ASIC designs, now provides full support for the Open Verification ...
Design-Reuse

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog SAN JOSE, Calif., & WILSONVILLE, Ore. -- August 16, 2007-- ...