Experienced designers of 10 Gbits/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/8GFC) products are well aware that the maintenance of signal quality is far more difficult ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs ...

Have you heard recommendations to use a particular termination in particular situations for good signal integrity? Have you ever wondered how to incorporate terminations in your design? While there ...

New clock fanout buffers claim to feature timing precision critical for high-speed infrastructure serving artificial intelligence (AI), cloud computing, and 5G/6G networks. These ultra-low jitter ...

Are you designing a board with high-speed chipsets on either end of the link? You own the interconnect—and the risk. As clock and data rates climb, maintaining signal integrity becomes critical for ...

Signal and power integrity have become pivotal concerns as data center and aerospace and defense products grow more complex and operate at higher frequencies. For Benjamin Dannan, the foundation of ...